Semiconductor devices, such as transistors, can be formed on silicon substrates. A transistor, for example, includes a source, a drain, and a gate formed in or on a silicon substrate. The source and drain may be formed by creating doped regions in the silicon, and the gate may be polysilicon deposited on the substrate. An insulating layer may be deposited over the substrate and the transistors formed in the substrate to insulate the active regions of the substrate. In order for the semiconductor device to function, electrical connections are made with the various components of the transistor. Portions of the insulating layer may be removed to provide access to the substrate and semiconductor devices below.
FIGS. 1A-C illustrate a prior art flash memory cell array 100. FIG. 1A illustrates an overhead view of a flash memory cell array 100. The array 100 shows a portion of a typical NOR flash memory cell array. The array 100 includes several drain contacts 102 and several source contacts 104. The contacts 102 and 104 may comprise a conductive material such as tungsten. The gates for the transistors are connected through word lines 106, and the drains for the transistors are connected through bit lines 108. In order to program or erase a specific cell, a signal is sent down the appropriate word line and bit line. For example, to program or erase the memory cell connected to the contact 102a, a pulse is sent through the bit line 108a and through the word line 106a, coupled through the common source rail via source contact 104a and source strap 108d. 
FIG. 1B illustrates a cross-sectional view of the array 100. As can be seen in FIG. 1B, the word lines 106 connect the control gates required for the memory cell, and are located over the floating gates 110. There is an interpoly oxide layer such as an oxide/nitride/oxide (ONO) dielectric layer between the gates to provide isolation and a tunnel oxide between the substrate 112 and the floating gates 110. FIG. 1C illustrates another cross-sectional view of the array 100. The layer 108 is typically either an etched aluminum metal pattern or a copper-filled trench using a damascene process. The isolation trenches 114 run through the substrate 112 and separate the diffusion regions 116 in the substrate 112.
The contacts 102 and 104 may be formed using a self-aligned contact (SAC) process. This technique typically involves forming an insulating shield layer of silicon nitride (Si3N4) over and around the gates. Another insulator layer of silicon dioxide (SiO2) is then deposited on the gate and substrate. A hole is then patterned and etched into the silicon dioxide layer, forming an SAC well that adjoins the silicon nitride barrier layer and exposes an area of the source or drain pocket. A contact material may then be deposited in the contact well to form an electrical contact to the source or drain pocket.
As can be seen in FIG. 1A, the contacts 102 and 104 are rectangular and the length and width of the openings are comparable in size. To form the openings required for the rectangular contacts, two-dimensional mask patterning must be used. However, accurately imaging two-dimensional patterns can be difficult as feature size is reduced. FIGS. 2A and 2B illustrate views of openings formed in an interlayer dielectric (ILD). FIG. 2A illustrates an overhead view of the ILD 200. FIG. 2B illustrates a cross sectional view of the ILD 200. Several openings 202 are formed in the ILD 200. The openings 202 provide access to semiconductor features on a substrate and will later be filled with a conductive material to create contacts. As can be seen, a recessed portion 204 between the openings 202 has inadvertently been created. The lines 206 illustrate the intended shape of the openings 202. Small feature size can lead to the inability to accurately image two dimensional masks.